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ZL10039 Digital Satellite Tuner with RF Bypass
Data Sheet Features
* * * * * * * * * * Direct conversion tuner for quadrature down conversion from L-band to Zero IF Symbol rate 1-45 MSps Excellent sensitivity <-84.5 dBm at 27.5 MSps Independent RF AGC and baseband gain control Fifth order baseband filters with bandwidth adjustable from 6 to 43 MHz Fully integrated alignment-free low phase noise local oscillator Selectable RF Bypass I2C compatible control 3.3 Volt Supply 28 pin 5x5 mm QFN Package Ordering Information ZL10039LCG ZL10039LCF ZL10039LCG1 ZL10039LCF1 *Pb 28 Pin QFN Trays 28 Pin QFN Tape and Reel 28 Pin QFN* Trays 28 Pin QFN* Tape and Reel Free Matte Tin
July 2005
-10C to +85C
Description
The ZL10039 is a fully integrated direct conversion tuner for digital satellite receiver systems, targeted primarily at free-to-air DVB-S receivers where high sensitivity is a priority. The device also contains a RF Bypass for connecting to a second receiver module. The ZL10039 is simple to use, requiring no alignment or tuning algorithms and uses a minimum number of external components. The device is programmable via a I2C compatible bus. A complete reference design (ZLE10541) is available using ZL10313 demodulator.
Applications
* * DVB-S Free-to-Air Satellite receiver systems 8PSK Satellite Receiver Systems
RF AGC
ZL10039
I
RF Input Q
Bypass Output
Quadrature
I2C Control
VCO
PLL
Loop
Filter
Crystal
Figure 1 - Basic Block Diagram 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved.
ZL10313 QPSK Demodulator
ZL10039 Table of Contents
Data Sheet
1.0 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2.1 RF Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2.2 Baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2.3 RF bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 Local Oscillator Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3.1 On Chip VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3.2 PLL Frequency Synthesiser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.0 Register Map and Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 PLL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 RF Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 Base Band Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 Local Oscillator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 General Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.0 Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.0 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.0 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.0 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.0 Typical Performance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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Zarlink Semiconductor Inc.
ZL10039 List of Figures
Data Sheet
Figure 1 - Basic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3 - Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 4 - Typical Application with ZL10313 Demodulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 5 - Gain v. RFAGC at 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 6 - Gain v RFAGC v. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 7 - IIP3 v Gain at 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 8 - IIP3 v Gain v Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 9 - IIP2 v Gain at 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 10 - IIP2 v Gain v Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 11 - Noise Figure v Freq at 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 12 - Noise Figure v RFin v Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 13 - LO Phase Noise at 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 14 - LO Phase Noise v Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 15 - RFin, RF Bypass Return Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 16 - RF Bypass Gain v Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 17 - Baseband Filter Response 26.5 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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Zarlink Semiconductor Inc.
ZL10039
SLEEP IOUT VccBB QOUT QOUT
Data Sheet
SDA P0 XCAP XTAL VccDIG VccCP PUMP
SCL
IOUT
RFAGC N/C N/C
ZL10039
1
PAD/REF VccLO RFBYPASS VccVCO Vvar LOTEST VccRF2
N/C RFIN N/C VccRF1
Ground - Package Paddle
Figure 2 - Pin Diagram
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Name Vvar PAD/REF VccVCO VccLO LOTEST VccRF2 VccRF1 N/C RFIN N/C N/C N/C RFAGC
Description LO Tuning Voltage Vvar Reference Ground / Continuity Test VCO Supply LO Supply LO Test pin - do not connect RF Supply RF Supply Not connected RF Input Not connected Not connected Not connected RF Gain control input
Pin # 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Name QOUT QOUT VccBB IOUT IOUT SLEEP SCL SDA P0 XCAP XTAL VccDIG VccCP PUMP
Description Q Channel baseband output Q Channel baseband output Baseband Supply I Channel baseband output I Channel baseband output Hardware power down input I2C Clock I2C Data General purpose switching output Crystal oscillator feedback Crystal oscillator crystal input Digital Supply Varactor Tuning Supply PLL charge pump output
RFBYPASS RF Bypass output
Table 1 - Pin Names
Note: Ground contact is via underside of package. Pin 2 is connected to ground internally.
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Zarlink Semiconductor Inc.
ZL10039
Data Sheet
BF
BANDWIDTH ADJUST VccBB
QOUT VccRF1 VccRF2 FILTER QOUT
RFAGC
DC CORRECTION
DC CORRECTION RFIN LNA AGC IOUT FILTER IOUT
90 deg
RFBYPASS
0 deg
PHASE SPLITTER VccLO LOTEST Vvar PAD/REF VccVCO
(PADDLE)
LOCK DETECT VCO BANK 15 BIT PROGRAMMABLE DIVIDER Fpd CHARGE PUMP PUMP
VccCP
VccDIG
Fcomp
SDA SCL
I2C BUS INTERFACE
PORT INTERFACE
P0
SLEEP XTAL XCAP
REF OSC
REFERENCE DIVIDER
Figure 3 - Detailed Block Diagram
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Zarlink Semiconductor Inc.
ZL10039
1.0
1.1
Data Sheet
Circuit Description
Functional Description
The ZL10039 is a single chip wide band direct conversion tuner with integral RF bypass optimised for digital satellite receiver systems. It provides excellent performance in applications where maximum sensitivity is required. The device offers a highly integrated solution for a satellite tuner incorporating a low phase noise PLL frequency synthesiser, the quadrature down converter, a fully integrated local oscillator, and programmable baseband channel filters. A minimal number of additional peripheral components are required. The crystal reference source can be also used as the reference for the demodulator. An I2C compatible bus interface controls all of the tuner functionality. The ZL10039 contains both hardware and software power down modes.
1.2 1.2.1
Signal Path RF Input
The tuner RF input signal at a frequency of 950 - 2150 MHz is fed to the ZL10039 RF input pre-amplifier stage. The signal handling is designed such that no tracking filter is required to offer immunity to input signal composite overload. The RF input amplifier feeds an AGC stage, which provides RF gain control. There is additional gain adjustment in the baseband section. The total AGC gain range will guarantee an operating dynamic range of -92 to -10 dBm. The RF AGC in the ZL10039 is a continually variable gain control stage, and provides the main system AGC set under control of the analogue AGC signal generated by the demodulator. The analogue RF AGC is optimised for S/N and S/I performance across the full dynamic range. Typical RF AGC characteristic and variation of IIP3, IIP2 and NF are shown in Section 8 - Typical Performance Curves. The output of the AGC stage is coupled to the quadrature mixer where the RF signal is mixed with quadrature local oscillator signals generated by the on-board local oscillator.
1.2.2
Baseband
The outputs of the quadrature down converter are passed through the baseband filters followed by a programmable baseband gain stage. The baseband paths are DC coupled. An integrated DC correction loop prevents saturation due to local oscillator self-mixing in the converter section. No external components are required for dc correction. The baseband filters are 5th order Chebychev and provide excellent matching in both amplitude and phase between the I and Q channels. The filters are fully programmable for 3 dB bandwidths from 6 MHz to 43 MHz. The recommended filter bandwidth is related to the required symbol rate by the following equation.
- 3dBFilterBandwidth fc =
SymbolRate x 1.35 2 x 0.8
This equation makes no allowance for LNB tuning offset at low symbol rates < 10MS/s. The baseband filter uses an automatic tuning algorithm to calibrate the filter bandwidth to the programmed requirement. This removes any variation due to operating conditions and process variations. The automatic tuning
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Zarlink Semiconductor Inc.
ZL10039
Data Sheet
algorithm uses a frequency locked loop, which locks the filter bandwidth to a reference frequency derived from the crystal reference input frequency. Further details are provided in the programming section. The filters are followed by a programmable gain stage. This provides twelve 1.5 dB gain steps. These can be used for optimising performance at different symbol rates and for adjusting the output level in applications not using ZL10313. The differential outputs of each channel stage are designed for low impedance drive capability and low intermodulation.
1.2.3
RF bypass
The ZL10039 provides a single ended bypass function, which can be used for driving a second receiver module. The electrical characteristics of the RF input are unchanged whether the RF bypass is enabled or disabled. The RF Bypass powers up in the enabled state and can also operate with the remainder of the device in power down modes.
1.3 1.3.1
Local Oscillator Generation On Chip VCO
The local oscillator on the ZL10039 is fully integrated. It consists of three independently selectable oscillator stages with sub bands. The three oscillators and sub-bands are designed to provide optimum phase noise performance over the required tuning range of 950 to 2150 MHz, over operating conditions and process variations. The local oscillators operate at a harmonic of the required local oscillator frequency and are divided down to the required LO frequency. The required divider ratio is automatically selected by the local oscillator control logic. The oscillators are fully controlled by an on-chip automatic tuning algorithm. The user simply programs the required LO frequency. The control logic automatically selects the required VCO and sub band to give optimum performance. VCO settling time is minimized as different tuning algorithms are used, depending on the magnitude of the LO frequency change required. This choice of algorithm is also automatic and does not require user intervention. The oscillator control logic tracks any changes in operating conditions and will retune the VCO if necessary, however hysteresis is built into this function to avoid unnecessary switching. All oscillator components are included on the chip including the VCO varactor. An external loop filter is required as part of the PLL frequency synthesiser.
1.3.2
PLL Frequency Synthesiser
The fully integrated PLL frequency synthesiser section controls the LO frequency. The only external requirements are crystal reference and simple second order loop filter. The PLL can be operated up to comparison frequencies of 2 MHz enabling a wide loop bandwidth for maximizing the close in phase noise performance. The local oscillator input signal is multiplexed from the active oscillator to an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier provides the input to a 15-bit fully programmable divider with MN+A architecture incorporating a dual modulus 16/17 prescaler. The output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. This frequency is derived either from the on-board crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider, which is programmable into 1 of 15 ratios.
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Zarlink Semiconductor Inc.
ZL10039
Data Sheet
The output of the phase detector feeds a charge pump which combined with an external loop filter integrates the current pulses to control the varactor voltage. The charge pump current is automatically varied by the VCO control logic to compensate for VCO gain variations that are dependent on selected sub band. The varactor control voltage is externally coupled to the oscillator section through the input pin Vvar.
1.4
I2C Interface
All programming for the ZL10039 is controlled by an I2C data bus and is compatible with 3V3 standard mode formats. Data and Clock are fed in on the SDA and SCL lines respectively as defined by I2C bus format. The device can either accept data (write mode), or send data (read mode). The LSB of the address byte (R/W) sets the device into write mode if it is logic `0', and read mode if it is logic `1'. The I2C address is fixed at C0 (Write)/C1(Read) in hex format. The ZL10039 contains 16 control registers. These registers are read/write registers. These registers are addressed as sub-addresses on the I2C bus. Registers can be addressed as random access single write/read or random access sequential write and read as shown below. Random Access Single Write
Stop Start Device W A Address Register Address N A Register Data N A Stop
Random Access Sequential Write
Stop Start Device W A Address Register Address N A Register Data N A Register Data N+1 ... Register Data N+M A Stop
Stop
Random Access Single Read
Stop Start Device W A Address Register Address N A Start Device Address R A Register Data N N Stop
Random Access Sequential Read
Stop Start Device W A Address Register Address N A Start Device Address R A Register Data N A ... Register Data N+M N Stop
W A N
Write bit Acknowledge Bit Not Acknowledge
A SLEEP pin is provided. This powers down all sections of the chip including the crystal oscillator and I2C interface. The RF bypass function will be operational in this mode providing it has been previously enabled through the I2C interface.
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ZL10039
2.0 Register Map and Programming
Data Sheet
The register map is arranged as 16 byte-wide read/write registers grouped by functional block. The registers may be written to and read-back from either sequentially (for lowest overhead) or specifically (for maximum flexibility). A significant number of bits are used for test and evaluation purposes only and are fixed at logic `0' or `1'. The correct programming for these test bits is shown in the table below. It is essential that these values are programmed for correct operation. When the contents of the registers are read back the value of some bits may have changed from their programmed value. This is due to the internal automatic control which can update registers. Any changes can be ignored. Read only bits are marked with an asterisk (*). Any data written to these bits will be ignored. Registers are set to default settings on applying power. These conditions are shown below and in the applicable tables. Register 0 1 2 3 4 5 6 7 8 9 A B C D E F PLL PLL PLL PLL RF Front End Base Band Base Band Base Band Local Oscillator Local Oscillator Local Oscillator Local Oscillator Local Oscillator Local Oscillator Local Oscillator General Block PLF 27 0 X* X* BF7 0 BLF* FLF* 1 1 X* 1 X* X* PD 214 26 0 1 1 BF6 LF BG3 0 0 1 X* 1 X* X* CLR 213 25 C1 0 1 BF5 SF BG2 1 1 1 1 0 X* 1 P0 Function 212 24 C0 0 0 BF4 BR4 BG1 0 0 1 1 1 1 1 0 211 23 R3 0 1 BF3 BR3 BG0 0 0 0 1 0 0 0 ZI3* 210 22 R2 0 1 BF2 BR2 0 0 0 0 0 0 0 0 ZI2* 29 21 R1 0 LEN BF1 BR1 0 0 1 0 0 0 0 0 ZI1* 28 20 R0 0 0 BF0 BR0 0 0 0 1 0 0 0 0 ZI0*
Table 2 - Register Map X* denotes a read only test bit
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Zarlink Semiconductor Inc.
ZL10039
2.1 PLL Registers
Data Sheet
There are four registers that control the PLL: Bit Field 7 6:0 Name PLF 2[14:8] Default 0 Type R R/W PLL Lock Flag MSB bits of LO Divider register Description
Table 3 - Register 0 The PLF bit is the PLL lock detect circuit output. The PLF bit is set after 64 consecutive comparison cycles in lock. A chip-wide reset initializes the lock detect output to 0. The 2[14:8] bits are the MSB bits of the LO Divider divide value.
Bit Field 7:0
Name 2[7:0]
Default 0
Type R/W Table 4 - Register 1
Description LSB bits of LO Divider register
The 2[7:0] bits are the LSB bits of the LO Divider divide value. The division ratio of the LO divider is fully programmable to integer values within the range of 240 to 32767. Note that when the LO Divider divide value is to be changed, the new value is not actually presented to the LO Divider until all of the 15-bit control word 2[14:0] has been programmed. Register 0 and 1 must be therefore be programmed (in any order) before the LO divider is updated even if the only data change is in one of the registers. Bit Field 7:6 5:4 3:0 Name C[1:0] R[3:0] Default 0 0 0 Type R/W R/W R/W Test modes Charge pump current Reference divider ratio Description
Table 5 - Register 2 The C[1:0] bits set the programmed charge pump current. C[1] 0 0 1 1 C[0] 0 1 0 1 Typ 400 550 750 1000 Units uA uA uA uA
Table 6 - Charge Pump Currents The charge pump current is automatically increased to the next setting dependent on the VCO sub band that has been selected by the VCO tuning algorithm. This is to compensate for changes in VCO gain and so provide consistent PLL performance across all sub bands. Programming the highest charge pump value will not allow the value to be incremented, therefore this value should not be programmed. The value read back for the charge pump current is the actual value in use for the selected sub band.
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ZL10039
Data Sheet
The R[3:0] bits select the Reference Divider divide ratio. The ratio selected is not a simple binary power-of-two value but through a lookup table, see Table 7- PLL Reference Divider Ratios. Division Ratio 2 4 8 16 32 64 128 256 3 5 10 20 40 80 160 320
R3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Table 7 - PLL Reference Divider Ratios
Bit Field 7:0
Name -
Default 0X40
Type R/W Test Modes
Description
Table 8 - Register 3 This register controls test modes within the PLL. This should be programmed with the default settings.
2.2
RF Control Register
A single register controls RF programmability. Bit Field 7 6:2 1 0 Name LEN Default 11011 1 0 Type R R/W R/W R/W Test Modes Test Modes Bypass Enable Not used Description
Table 9 - Register 4
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Zarlink Semiconductor Inc.
ZL10039
Data Sheet
The LEN bit enables the RFBYPASS output. With this bit set, the RF Bypass is active even if `software' or `hardware' power down has been selected.
2.3
Base Band Registers
There are three registers that control the Base Band: Bit Field 7:0 Name BF[7:0] Default 0X3C Type R/W Description Base Band Filter Cut-Off Frequency
Table 10 - Register 5 The bits BF[7:0] control the bandwidth of the baseband filter. An automatic adjustment routine synchronizes the filter bandwidth to a reference frequency derived from the crystal. Bit Field 7 6 5 4:0 Name LF SF BR[4:0] Default 0 0 0 1000 Type R/W R/W R/W R/W Test Mode Baseband Filter Adjust Disable Baseband Filter Adjust Disable Base Band Reference Division Ratio Description
Table 11 - Register 6 The LF and SF bits disable the baseband filter adjustment. It is recommended that these bits are set after programming the filter bandwidth to prevent interactions within the circuit. These bits must be reset to enable the baseband filter bandwidth to be reprogrammed. The BR[4:0] bits set the crystal reference divide ratio. This effectively determines the resolution setting of the baseband filters. The baseband filter settings (BF[7:0]) can be calculated from the following equation.
BF[7 : 0] =
(Filter bandwidth (MHz) * 5.088 * BR[4 : 0]) -1 CrystalFrequency (MHz)
See Section 3 Applications Information, for a typical programming example. BR[4:0] = 0 is invalid Bit Field 7 6:3 2:0 Name BLF BG[3:0] Default 0111 000 Type R R/W R/W Description Base Band Lock Flag Base Band Gain Select Test Modes
Table 12 - Register 7 The BLF bit indicates that the baseband adjustment has completed and locked. The control bits BG[3:0] define the gain of the Base Band post-filter amplifier. The following table shows the gain note this is relative gain. The 1.5 dB gain steps enable the baseband output level to be adjusted and optimise gain distribution for different symbol rates.
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Zarlink Semiconductor Inc.
ZL10039
BG[3] 0 0 0 0 0 0 0 0 1 1 1 1 BG[2] 0 0 0 0 1 1 1 1 0 0 0 0 BG[1] 0 0 1 1 0 0 1 1 0 0 1 1 BG[0] 0 1 0 1 0 1 0 1 0 1 0 1 Gain (dB) 0 1.5 3.0 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 16.5
Data Sheet
Table 13 - BG[3:0] Control of Base Band Post Filter Gain
2.4
Local Oscillator Registers
There are seven registers that control the Local Oscillator: These are used primarily for test and evaluation by Zarlink Semiconductor. Although VCO's can be manually programmed, the user is recommended to use the default automatic settings as these provide optimum performance. Bit Field 7 6:0 Name FLF Default 0X20 Type R R/W Full Lock Flag Test Modes Description
Table 14 - Register 8 The FLF bit is the VCO tuning controller lock output and is set when PLL is locked and the automatic VCO tuning is optimised and complete. Register 9 to Register E are for test modes only. It is however important that these registers are programmed with the values shown.
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ZL10039
Bit Field 7:0 Name Default 0XA2 Type R/W Test Modes Description
Data Sheet
Table 15 - Register 9 Bit Field 7:0 Name Default 0XF1 Type R/W Test Modes Description
Table 16 - Register A Bit Field 7:6 5:0 Name Default 0X38 Type R R/W Description Test Modes (read only) Test Modes
Table 17 - Register B Chip Level Control Register Bit Field 7:0 Name Default 0XD0 Type R/W Test Modes Description
Table 18 - Register C Bit Field 7:5 4:0 Name Default 0X10 Type R R/W Description Test Modes (read only) Test Modes
Table 19 - Register D Bit Field 7:6 5:0 Name Default 0X30 Type R R/W Description Test Modes (read only) Test Modes
Table 20 - Register E
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Zarlink Semiconductor Inc.
ZL10039
2.5 General Control Register
Data Sheet
This register controls powerdown and general control functions: Bit Field 7 6 5 4 3:0 Name PD CLR P0 ZI3:0Default 1 0 0 0 Type R/W R/W R/W R/W R Power Down Clear and reset logic Port 0 control Test Mode Zarlink identity code (read only) Description
Table 21 - Register F The PD bit is the `software' power down control. When this bit is set to 1, all the analogue blocks are powered down with the exception of the Crystal Oscillator. The I2C interface will remain active and can still be used to enable the RF Bypass. Setting the SLEEP input pin high also invokes `software' power down with the addition of powering down the Crystal Oscillator to produce `hardware' power down. The RF Bypass will remain active if it has been previously programmed on the I2C bus. Note that in `hardware' power down, the I2C interface does not operate. The CLR bit re-triggers the power-on-reset function. This resets all register values to their power-on reset default value. The CLR bit is itself cleared. Note that the chip-wide reset will reset the I2C Interface and the current write sequence used to set this bit will not be acknowledged. The P0 bit controls the state of the output port according to Table 22. P0 0 1 Output Port State Off, high impedance On, current sinking
Table 22 - Output Port States
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Zarlink Semiconductor Inc.
ZL10039
3.0 Applications Information
Data Sheet
Figure 4 - Typical Application with ZL10313 Demodulator
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Zarlink Semiconductor Inc.
ZL10039
Data Sheet
Figure 4 shows a typical application using a ZL10313 as a demodulator. This is available as a reference design (ZLE10541) from Zarlink Semiconductor. The design uses a standard two layer board. All components are mounted on the upper surface with the lower surface as a ground plane. The RF input does not require any external matching components although a coupling capacitor is required. The RF bypass output requires a series inductor for optimum matching. Good decoupling should be used - these components should be mounted as close to the device as practicable. All ground contact to the ZL10039 is to the ground `paddle' on the underside of the package. This must be soldered fully to the board to achieve best thermal and electrical contact. It is recommended that an array of vias (4 x 4) is used to achieve good contact to the ground plane underneath the device A common crystal reference can be used for the tuner and demodulator. The crystal oscillator capacitors are optimised for a 10.111 MHz reference. Sensitivity is optimised by minimizing interaction from digital signal activity in the demodulator. This is achieved by filtering in the agc control, and filter networks in the baseband I and Q signals between the demodulator and ZL10039. These networks should be mounted as close to the ZL10039 as possible. The typical performance from the reference design is shown in the table below: Parameter Sensitivity C/N 27.5MS/s rate 7/8 2e-4 post Viterbi BER C/N 2MS/s rate 7/8 2e-4 post Viterbi BER Interference Rejection Ratio 27.5 MS/s rate 7/8. Interferers at -25 dBm 8.2 8.1 8.1 8.1 8.0 8.0 32 35 45 Typ. Units dBm dB dB dB dB dB dB dB dB dB Notes QEF 27.5MS/s rate 7/8 No added noise Input = -69 dBm -45 dBm -23 dBm Input = -81dBm -45 dBm -23 dBm N+1 N+4 N+10
Table 23 - Typical Performance using ZL10039and ZL10313 Further information is provided in ZLE10541 user guides.
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Zarlink Semiconductor Inc.
ZL10039
The bandwidth of the baseband filter is given by the following expression:
fbw = fxtal x (BF + 1) BR x 5.088
Data Sheet
Equation 1
where: fbw fxtal BR = = = the filter bandwidth in MHz within the range 8 MHz to 43 MHz. crystal oscillator frequency in MHz. decimal value of the bits BR[4:0], range 1-31. (BR = 0 is not allowed) BF = decimal value of the register bits BF[7:0], range 0 - 255.
BR BF = fbw x 5.088 x -1 fxtal
The above equation can be re-arranged as follows Equation 2
fxtal BR
It is recommended that BR should be set so that
is approximately 1 MHz
This sets the bandwidth resolution to approximately 200kHz The value of BF can now be calculated from Equation 2 and rounded to the nearest integer: Example Conditions: fxtal = 10.111 MHz, fbw = 26.5 MHz Choose BR = 10
BF = 26.5 x 5.088 x 10 - 1 = 132.35 10.111
BF = 132 The actual filter bandwidth is therefore given by:
fbw = 1 10.111 x (132 + 1) x = 26.43 MHz 5.088 10
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Zarlink Semiconductor Inc.
ZL10039
4.0
Pin# 1
Data Sheet
Pin Descriptions
Name Vvar Description LO voltage tuning input.
Vvar
Schematic
100
Components per VCO Vbias
2
PAD/REF
Bonded to paddle. Production continuity test for paddle soldering and also ground reference for loop filter. +3.3 V voltage supply for VCO's. +3.3 V voltage supply for LO circuits. For Zarlink testing only. Must not connect. RF bypass output. AC couple. Matching circuitry as shown in applications diagram. Do not connect in applications where RF bypass is not required.
3 4 5 6
VccVCO VccLO LOTEST RFBYPASS
120
RFBYPASS
7 8 9 10
VccRF2 VccRF1 N/C RFIN
+3.3 V voltage supply for RF. +3.3 V voltage supply for RF. Not connected. RF input. AC couple. See applications diagram.
Vcc
RFIN
11 12 13
N/C N/C N/C
Not connected. Not connected. Not connected.
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Zarlink Semiconductor Inc.
ZL10039
Pin# 14 Name RFAGC Description RF analog gain control input.
Vcc Vref 10k RFAGC 30k
Data Sheet
Schematic
15 16
QOUT QOUT
Q channel baseband differential outputs. AC couple as shown in application diagram.
Vcc
Output
17 18 19
VccBB IOUT IOUT
+3.3 V voltage supply for Baseband. I channel baseband differential outputs. AC couple as shown in application diagram. Hardware power down input. Logic '0' normal mode. Logic '1' - analog sections are powered down including crystal oscillator. Same as pin 15,16
20
SLEEP
SLEEP
CMOS Digital input
21
SCL
I2C serial clock input
SCL
CMOS Digital input
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Zarlink Semiconductor Inc.
ZL10039
Pin# 22 Name SDA Description I2C serial data input/output
SDA
Data Sheet
Schematic
CMOS Digital input/output
23
P0
Switching port output. Open Drain '0' = disabled (high impedance) '1' = enabled.
CMOS Digital output
P0
24 25
XCAP XTAL
Reference oscillator crystal inputs. XTAL pin can be used for external reference via 10nF capacitor. See applications diagram for recommended external components (10.111 MHz)
Vcc
100
XTAL
XCAP
0.2 mA
26 27 28
VccDIG VccCP PUMP
+3.3 V voltage supply for digital logic. +3.3 V voltage supply for varactor tuning. Charge pump output.
Vcc
PUMP
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Zarlink Semiconductor Inc.
ZL10039
5.0 Absolute Maximum Ratings
Parameter Maximum voltage on any Vcc pin Maximum voltage between any two Vcc pins Maximum voltage on any other pin P0 Output current Maximum RF Input Storage temperature Junction temperature Package thermal resistance ESD Protection -55 -0.3 Min. -0.3 Max. 3.6 0.3 Vcc + 0.3 20 10 150 125 34 1.75 Units V V V mA dBm C C C/W kV Package ground paddle soldered to ground Mil std 883B method 3015 cat1 Notes
Data Sheet
The voltage on any pin must not exceed 3.6 V
6.0
Operating Conditions
Parameter Min. 3.15 -10 950 4.7 15 Max. 3.45 +85 2150 Units V C MHz k pF Notes
Supply Voltage Operating Temperature RF Input Frequency Baseband I/Q Output load
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Zarlink Semiconductor Inc.
ZL10039
7.0 Electrical Characteristics
Data Sheet
Test conditions (unless otherwise stated) Tamb = 25oC, Vee= 0V, All Vcc supplies = 3.3 V+-5% Baseband Gain = 9 dB Baseband filter bandwidth 26.5 MHz All power levels are referred to 75 (0 dBm = 109 dBV) Specifications refer to total cascaded system of converter/AGC stage and baseband amplifier/filter stage. Output amplitude of 0.5 Vp-p differential. Characteristic Supply Current 145 155 Hardware Power Down Software Power Down System Input Return Loss Noise Figure DSB 7 9 6 7 9 10 13 -1 -92 -84 72 68 -150 78 -10 72 150 -23 -30 -26 -38 5 -5 -10 -10 dB dB dB dB dB/dB dBm dBm dB dB dB A dBc dBc dBc dBc dBm dBm Zo = 75 . Bypass enabled or disabled At max gain At -70 dBm operating level At -60 dBm operating level Above -60dBm operating level 1MS/s 27.5MS/s RFagc = 0.2V RFagc = 2.8V AGC monotonic for RFagc from Vee to Vcc Vee <= RFagc<= Vcc Baseband defined, note 1 RF front-end defined, note 2 Note 3 Note 4 At -25 dBm input, note 2 At -25 dBm input, note 3 0.2 1.7 200 215 3 mA mA mA mA Min. Typ. Max. Units Conditions Outputs unloaded. Max Filter bandwidth RF Bypass disabled RF Bypass enabled No RF input. Crystal oscillator remains operational
Variation in NF with RF gain adjust Operating dynamic range Operating dynamic range Conversion Gain Max Min AGC Control Range RFAGC input current System IM2 System IM3 IIP2 IIP3
10
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Zarlink Semiconductor Inc.
ZL10039
Characteristic Variation in system second order intermodulation intercept Variation in system third order intermodulation intercept LO second harmonic interference level Quadrature gain match Quadrature phase match I & Q channel in band ripple LO reference sideband spur level on I & Q outputs In band local oscillator leakage to RF input Channel lock time Local Oscillator VCO Gain SSB Phase Noise 27 -83 -76 -96 -110 -132 3 -10 6 -1 10 43 +1 10 -30 MHz/V dBc/Hz dBc/Hz dBc/Hz dBc/Hz deg nA MHz MHz ms dBc 10 kHz to 15 MHz Vvar = 0.5 to 1.3 V Max specified load All bandwidth settings LO = 2 GHz. Note 8 10 kHz offset 100 kHz offset 1 MHz offset -1 -3 -5 -50 Min. Typ. Max. -1 Units dB/dB Note 5 Conditions
Data Sheet
-1
dB/dB
Note 6
-35 1 3 5 1 -40 -65 -55 50
dBc dB deg deg dB dBc dBm dBm ms
Note 7, all gain settings 1.5 to 18 MHz Baseband Signal = 1.5 MHz Baseband Signal = 18 MHz 1.5 to 18 MHz Synthesiser phase detector comparison frequency 500 - 2000 kHz 950 - 2150 MHz 30 - 950 MHz Worst case channels
Phase Noise floor Integrated phase jitter Varactor input current Baseband Filters Bandwidth Bandwidth Tolerance Time to change filter bandwidth Total Harmonic Distortion RF Bypass Gain Noise Figure OPIP3 OPIP2 10 5 -2 1.5
1 Vpp differential output at 43 MHz filter bandwidth Output load = 75 ohms
6 10
dB dB dB dBm Note 9 Note 10
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Zarlink Semiconductor Inc.
ZL10039
Characteristic Output return loss Forward Isolation Reverse Isolation In band LO leakage Synthesiser Charge Pump Current 304 422 578 762 -10 0.4 4 12 25 100 16 10 4 0.5 0.5 -148 20 2.0 2 400 550 750 1000 2 +/-3 +10 Vcc - 0.4 20 50 500 552 759 1035 1380 A A A A % nA V MHz ohms W pF ms MHz Vpp MHz dBc/Hz ac coupled sinewave ac coupled sinewave 10 MHz crystal Note 11 Note 11 Vpin = 0.5 to 1.3 V Vpin = 0.5 to 1.3 V Min. 9 25 25 -65 Typ. Max. Units dB dB dB dBm Conditions
Data Sheet
950-2150 MHz. Bypass disabled 950-2150 MHz. Bypass enabled or disabled 950-2150 MHz. Bypass enabled or disabled
Charge Pump Matching Charge Pump Leakage Charge Pump Compliance Crystal Frequency Recommended crystal series resistance Crystal power dissipation Crystal load capacitance Crystal oscillator startup time External reference input frequency External reference drive level Phase detector comparison frequency Equivalent phase noise at phase detector Interface SDA, SCL Input high voltage Input low voltage Hysteresis Input current SDA Output Voltage SCL clock rate 2.3 0
10 MHz crystal SSB within PLL loop bandwidth
3.6 1 0.4 10 0.4 100
V V A V kHz Input = Vee to VccDIG +0.3 V Isink = 3 mA
-10
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Zarlink Semiconductor Inc.
ZL10039
Characteristic External Port P0 Sink Current Leakage Current SLEEP Input Input high voltage Input low voltage Input Current
Note 1: Note 2:
Data Sheet
Conditions Vo = 0.7 V Vo = Vcc
Min. 3
Typ.
Max.
Units mA A V V A
10 1.9 Vee 3.6 1.0 10
Vin = Vee to VccDIG
AGC set to deliver an output of 0.5 Vp-p with an input CW @ frequency fc of -25 dBm, undesired tones at fc+146 and fc+155 MHz @ -18 dBm, generating output IM spur at 9 MHz. Measured relative to unwanted signal. LO set to 2145 MHz and AGC set to deliver a 5 MHz output of 0.5 Vp-p with an input CW @ frequency 2150 MHz of -25 dBm. Undesired tones at 1.05 and 1.1 GHz at -25 dBm generating IM spur at 5 MHz baseband. Measured relative to unwanted signal. AGC set to deliver an output of 0.5 Vp-p with an input CW @ frequency fc of -25 dBm. Two undesired tones at fc+205 and fc+405 MHz at -18 dBm, generating output IM spur at 5 MHz. AGC set to deliver an output of 0.5 Vp-p with an input CW @ frequency fc of -25 dBm. Two undesired tones at fc+205 and fc+405 MHz at -24 dBm, generating output IM spur at 5 MHz. Two undesired tones at 1.05 and 1.1 GHz at 0 dBc relative to desired at 2.15 GHz, Local oscillator tuned to 2.145 GHz with AGC set to deliver 0.5 Vp-p differential on desired signal. Desired input signal is varied from -25 dBm to -75 dBm. Two undesired tones at fc+55 and fc+105 MHz at 7 dBc relative to desired at fc converted to 5 MHz baseband with local oscillator tuned to fc GHz with AGC set to deliver 0.5 Vp-p differential on desired signal. Desired input signal is varied from -30 dBm to -75 dBm, with the undesired amplitude capped at -25 dBm. The level of 2.01 GHz down converted to baseband relative to 1.01 GHz with the oscillator tuned to 1 GHz. Reference VCO gain value for loop filter calculations. Using this recommended value then takes into account VCO switching and automatic charge pump current variations. Two input tones at fc+50 and fc+100 MHz at -18 dBm, generating output IM product at fc.
Note 3: Note 4: Note 5: Note 6:
Note 7: Note 8: Note 9:
Note 10: IM2 product from two input tones at 1.05 and 1.1 GHz at -18 dBm, generating IM product at 2150 MHz. Note 11: Crystal specifications vary considerably and significantly effect the choice of external oscillator capacitor values. Each application may require separate consideration for optimum performance.
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Zarlink Semiconductor Inc.
ZL10039
8.0 Typical Performance Data
80 70 60 Conversion gain dB 50 40 30 20 10 0 -10 -20 0 0.5 1 1.5 AGC Voltage 2 2.5 3 LO 920MHz LO 1550MHz LO 2150MHz
Data Sheet
Figure 5 - Gain v. RFAGC at 25C
80 70 60 Conversion gain dB 50 40 30 20 10 0 -10 -20 0 0.5 1 1.5 AGC Voltage 2 2.5 3 +90C +25C -15C
Figure 6 - Gain v RFAGC v. Temperature
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Zarlink Semiconductor Inc.
ZL10039
Data Sheet
20 Spec 10 0 -10 IIP3 dBm -20 -30 -40 -50 -60 20 30 40 50 60 70 80 Gain Setting dB 3.1Vcc 3.3Vcc 3.5Vcc
Figure 7 - IIP3 v Gain at 25C
20 Spec 10 0 -10 IIP3 dBm -20 -30 -40 -50 -60 20 30 40 50 60 70 80 Gain Setting dB +90C +25C -15C
Figure 8 - IIP3 v Gain v Temperature
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Zarlink Semiconductor Inc.
ZL10039
Data Sheet
40 Spec 30 20 10 IIP2 dBm 0 -10 -20 -30 -40 -50 20 30 40 50 60 Gain Setting dB 70 80 3.1Vcc 3.3Vcc 3.5Vcc
Figure 9 - IIP2 v Gain at 25C
40 Spec 30 20 10 IIP2 dBm 0 -10 -20 -30 -40 -50 20 30 40 50 60 Gain Setting dB 70 80 +90C +25C -15C
Figure 10 - IIP2 v Gain v Temperature
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Zarlink Semiconductor Inc.
ZL10039
Data Sheet
10 9.5 9 8.5 NF (dB) 8 7.5 7 6.5 6 5.5 5 950
1150
1350
1550
1750
1950
2150
Frequency (MHz)
Figure 11 - Noise Figure v Freq at 25C
50
40
30 NF (dB) 20 -15C 10 25C 90C Spec 0 -80 -70 -60 -50 -40 -30 -20 -10 RFin (dBm)
Figure 12 - Noise Figure v RFin v Temperature
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Zarlink Semiconductor Inc.
ZL10039
-70
Data Sheet
-80 Phase Noise (dBc/Hz)
-90
-100
-110
-120
-130 10000
100000
1000000
10000000
Frequency offset (Hz)
Figure 13 - LO Phase Noise at 25C
-80.0 -15degC -85.0 -90.0 Phase noise (dBc/Hz) -95.0 -100.0 -105.0 -110.0 -115.0 -120.0 1000 +90degC
10000
100000
1000000
Frequency offset (Hz)
Figure 14 - LO Phase Noise v Temperature
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Zarlink Semiconductor Inc.
ZL10039
Data Sheet
0.0 s11 RFBYPASS on s22 RFBYPASS on
-5.0
Return Loss (dB)
-10.0
-15.0
-20.0
-25.0
-30.0 950
1150
1350
1550
1750
1950
2150
Frequency (MHz)
Figure 15 - RFin, RF Bypass Return Loss
3.0 2.5 2.0 1.5 Gain (dB) 1.0 0.5 0.0 -0.5 -1.0 950 -15C +25C +90C
1150
1350
1550
1750
1950
2150
Frequency (MHz)
Figure 16 - RF Bypass Gain v Temperature
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Zarlink Semiconductor Inc.
ZL10039
Data Sheet
10 0 Normalised amplitude (dB) -10 -20 -30 -40 -50 -60 -70 -80 -90 0
26.5MHz filter response
+90C +25C -15C
40
80
120
Baseband frequency (MHz)
Figure 17 - Baseband Filter Response 26.5 MHz
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Zarlink Semiconductor Inc.
c Zarlink Semiconductor 2005 All rights reserved.
Package Code Previous package codes
LC
ISSUE ACN DATE APPRD.
1 CDCA 10June05
Package Outline for 28 Lead QFN (5 x 5mm) Full Connectiing Bar (FCB), VHHD-3 variant
LH
112083
For more information about all Zarlink products visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request.
Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved.
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